† Corresponding author. E-mail:
Project supported by the National Key Research and Development Program of China (Grant No. 2017YFB0402800), the Key Research and Development Program of Guangdong Province, China (Grant Nos. 2019B010128002 and 2020B010173001), the National Natural Science Foundation of China (Grant Nos. U1601210 and 61904207), the Natural Science Foundation of Guangdong Province of China (Grant No. 2015A030312011), and the China Postdoctoral Science Foundation (Grant No. 2019M663233).
We experimentally evaluated the interface state density of GaN MIS-HEMTs during time-dependent dielectric breakdown (TDDB). Under a high forward gate bias stress, newly increased traps generate both at the SiNx/AlGaN interface and the SiNx bulk, resulting in the voltage shift and the increase of the voltage hysteresis. When prolonging the stress duration, the defects density generated in the SiNx dielectric becomes dominating, which drastically increases the gate leakage current and causes the catastrophic failure. After recovery by UV light illumination, the negative shift in threshold voltage (compared with the fresh one) confirms the accumulation of positive charge at the SiNx/AlGaN interface and/or in SiNx bulk, which is possibly ascribed to the broken bonds after long-term stress. These results experimentally confirm the role of defects in the TDDB of GaN-based MIS-HEMTs.
GaN-based transistors on Si substrate emerged as promising candidates for high voltage, high frequency, and high power applications.[1] Especially, GaN-based metal–insulator–semiconductor (MIS) high electron mobility transistors (MIS-HEMTs) have attracting wide attention owing to the low gate leakage and large gate swing.[2–4] Nevertheless, the reliability issue of MIS-HEMTs caused by the introduction of gate insulator layer is still a major challenge before its commercialization.
One of the most critical gate reliability issues of MIS-HEMTs is the time-dependent dielectric breakdown (TDDB). To concentrate the electric-field in the gate stack, forward constant voltage stress (CVS) TDDB experiments have been conducted to evaluate the gate robustness of MIS-HEMTs.[5–9] Besides, Simon et al. investigated the dependence of the dielectric breakdown by forward biased constant current stress (CCS) TDDB measurements.[10] Until now, most of the previous literatures focus on using the catastrophic failure time to evaluate the lifetime of different gate structures, such as the thickness of the dielectric and AlGaN barrier,[6] the area scaling,[7] and the gate electrode.[10] Generally, it is accepted that newly increased traps will occur randomly in the gate stack by prolonging the high-voltage or current gate stress and eventually result in a catastrophic failure. However, there is rarely experimental evaluation to confirm this possible mechanism. In particular, the GaN-based MIS-HEMTs contain multiple layers and several interfaces, which complicates the physical origin of the time-dependent gate degradation.[11–13] Thus, in order to improve the gate reliability of GaN-based MIS-HEMTs effectively, a comprehensive gate degradation analysis of MIS-gate structure is very necessary.
In this paper, forward constant gate bias stress was conducted in low-pressure chemical vapor deposition (LPCVD) SiNx/AlGaN/GaN MIS-HEMTs to analyze the time-dependent interface state variation. Moreover, the understanding of gate degradation can provide reference for normally-off MISFETs with dielectric and thin AlGaN barrier layer.[14] The first section of this paper analyzed the gate leakage mechanism under forward bias through temperature-dependent gate current characteristics. Then, the gate degradation during the electric-field-accelerated TDDB experiment was discussed to determine the stress voltage and duration. Finally, a series of stress-time-dependent experiments were developed to understand the interface state variation, including current–voltage (I–V) and capacitance–voltage (C–V) characterizations.
The devices were fabricated on 6-inch (1 inch = 2.54 cm) Si substrate by an industry standard complementary metal–oxide–semiconductor (CMOS) process. The cross-sectional schematic diagram of LPCVD-SiNx/AlGaN/GaN MIS-HEMT is shown in Fig.
Figure
The temperature-dependent gate leakage current (IG–VGS) curves measured on the AlGaN/GaN MIS-HEMTs are shown in Fig.
![]() | Fig. 3. Temperature-dependent IG–VGS characteristics (a) and the corresponding Poole–Frenkel plots (b) of the LPCVD-SiNx/AlGaN/GaN MIS-HEMT. |
![]() | Fig. 4. The simulated energy band diagram of the LPCVD-SiNx/AlGaN/GaN MIS-structure under different forward gate biases. |
There are several gate leakage mechanisms for GaN-based MIS-gate structure. For example, thermionic emission, Poole–Frenkel (PF) emission, Fowler–Nordheim tunneling, and trap-assisted tunneling. According to our test results, when VGS is higher than 15 V, the gate leakage current depends on both gate bias and temperature, suggesting that the PF emission may be the dominating mechanism under relatively high gate bias. The PF emission can be expressed as the following formula[16]
The plots of ln(JPF/Eox) versus
Finally, an effective method to evaluate the gate reliability is the TDDB test. Herein, the forward gate bias TDDB measurements on LPCVD-SiNx/AlGaN/GaN MIS-HEMTs were conducted at room temperature with three different gate biases of 30 V, 32 V, and 34 V (around 70%–80% of VGS_max, ten devices per group), while source and drain were grounded, respectively. The gate leakage current was monitored during the stress experiment as shown in Fig.
In order to deeply understand the effect of forward gate bias stress on the interface state density, a time-dependent stress experiment was used based on the TDDB results. The test process is shown in the inset of Fig.
![]() | Fig. 6. The gate leakage variation during the whole stress experiment. Inset: the test process of the typical stress experiment, including stress interruption and device characterization. |
![]() | Fig. 7. Monitored output characteristics (a) and transfer characteristics (b) during the gate stress. Inset: on-resistance variation extracted from the output characteristics. |
Frequency conductance method (with frequency from 1 kHz to 100 kHz) was performed to estimate the traps density at LPCVD-SiNx/AlGaN interface (Dit) during the gate stress.[23] The Gp/ω–ω curves for the samples before and after 5000-s forward gate bias stress were recorded at selected bias in the deep accumulation region calculated from the second increase step of C–V curves (not shown). It can be observed that the Gp/ω peak shifts to the higher frequency side along with an increasing amplitudes, indicating the increase of Dit after gate stress. Figure
![]() | Fig. 8. The evolution of Dit versus EC–ET (a) at different stress time and the corresponding Dit integrated from EC–0.34 eV to EC–0.4 eV (b) during the gate degradation. |
Double sweep C–V measurements were also conducted at each test point to evaluate the variation of trap density during gate gradation. In order to avoid C–V curves clutter, only three double sweep C–V curves at test points of t = 0 s, 10 s, 5500 s are shown in Fig.
The hysteresis of Von is attributed to both LPCVD-SiNx/AlGaN interface states and LPCVD-SiNx dielectric bulk traps (Dbt), owing to the large maximum gate voltage in double sweep C–V measurements.[24] The traps density and increment of traps density can be respectively estimated according to
Besides, it worth noting that a slowly negative shift of Vth and Von in C–V curves is observed after the firstly positive shift caused by electron trapping, which is consistent with Fig.
To further investigate the effect of newly increased traps on the gate leakage current, the IG–VGS curves were also extracted during the gate degradation as shown in Fig.
![]() | Fig. 10. (a) The gate leakage characteristics measured during gate degradation. (b) The evolution of gate leakage current at VGS = 15 V was extracted from IG–VGS curves during the degradation. |
Finally, by introducing UV light illumination experiments (wavelength = 365 nm), the generation of positive charge at the LPCVD-SiNx/AlGaN interface and/or in LPCVD-SiNx layer was verified. Before the forward gate bias stress, the device was illuminated with UV light for ten minutes. There is no obvious difference in Vth and Von before and after UV light illumination, which is owing to the high interface quality of LPCVD-SiNx/AlGN. Then, the constant gate bias stress with VGS = 30 V was applied to accelerate the gate degradation. The transfer characteristics and C–V curves were monitored during the stress, and the test process is same with that shown in the inset of Fig.
In summary, we have experimentally investigated the physical origin of the time-dependent gate degradation in LPCVD-SiNx/AlGaN/GaN MIS-HEMTs under forward gate bias stress. Through the temperature-dependent gate current characteristics, the dominant mechanism of gate leakage current was identified to be PF emission which is a traps-assistant emission process under relatively high forward bias. During the forward gate bias stress, the stable output characteristics suggest that the degradation is concentrated in the gate dielectric region, instead of the AlGaN/GaN heterojunction. Combining with the frequency conductance method and double sweep C–V curves, the newly increased traps were observed not only in the LPCVD-SiNx layer but also at the LPCVD-SiNx/AlGaN interface, resulting in the voltage shift and the increase of the voltage hysteresis. Particularly, we found that the traps generated in the LPCVD-SiNx layer dominated the later stage of time-dependent gate degradation. Finally, the additional negative shift of Vth and Von after UV light illumination confirmed the accumulation of positive charge at the LPCVD-SiNx/AlGaN interface and/or in LPCVD-SiNx layer, which is consistent with the generation of newly increased traps.
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